Test and measurement is an important component of modern product development and manufacture. A class of test systems designed to perform these tests automatically are referred to as automated test equipment (ATE). Automated test equipment is typically programmed to automatically execute a number of selected tests on a specific circuit or component. The particular tests performed and the conditions under which they are performed is dependent upon the item being tested, the stage of product development, and the intended application.
An increasingly common packaging technology for electronic circuits is the so called “multi-chip-package (MCP)”. In multi-chip-packages several integrated circuit die are mounted together in a single package with the various die often interconnected internally within the package.
The testing of these multi-chip-packages by automated test equipment (ATE) has resulted in a new set of challenges. For instance, multiple die that have been traditionally tested in different test systems are now being integrated into a single package. Multiple insertion testing in different test systems has been used, but there is a penalty paid in the cost of equipment, in additional floor space, in the time required to test the package, in potential damage to the pins of the package, and in the reliability of the package following the multiple insertions.
Also, different types of die require different tester characteristics. A multi-chip-package could have, for example, chips with different types of memories, logic devices, analogue circuits, or even radio-frequency (RF) devices. Ideally these multi-chip-package devices can be tested using the least number of insertions, so that a given test system must be able to do more to perform tests having extra functionality.
Further, the total pin-count on common multi-chip-package devices is much greater than traditional memory chips. Even a pure memory multi-chip-package could have hundred's of pins depending on the manner in which signals are brought out of the package.
In addition, the desire for parallel testing continues to grow. Today a typical test system can test 32 devices under test (DUTs) in parallel. In the near future the testing of 64 devices in parallel is expected. And not too far in the future, machines will need to test 256 or more devices in parallel. This will result in an extraordinary number of test pins on the tester. For example a typical multi-chip-package device could have 384 pins. The total pin count at the interface between the tester and the DUT area for 256 devices in parallel would then be 384×256=98,384 pins per test system. The largest test system currently on the market has 4,608 pins.
In addition, chip speeds also continue to increase. Devices that can go into a multi-chip-package include chips that can run at high frequencies like DDR (Double Data Rate) and DDR2 or fast SRAM (Static Random Access Memory). Current multi-chip-packages include various die that can run up to 133 Mbit/second, but future packages will likely have 200 Mbit/second and 266 Mbit/second die. And, it is expected that the trend toward increased speed will continue.